1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a programming method therefor, and relates in particular to a nonvolatile semiconductor memory device (a flash memory) and a programming method therefor.
2. Description of Related Arts
At present, various types of nonvolatile semiconductor memory devices, such as mask ROMs, EEPROMs and flash memories, are available. Of these devices, an electrically rewritable flash memory that is appropriate for high integration has drawn the attention of many people (see Japanese Unexamined Patent Publication No. Hei 6-275842). For nonvolatile memory, in principle, one transistor constitutes one memory cell, and since basically no selection transistors are required and a memory cell occupies only a small area, originally the data held by a single memory cell could not be erased. Now, however, with flash memory, data erasing is performed collectively by blocks.
Memory cells (a circuit) in a flash memory are shown in FIG. 11. In FIG. 11, a source voltage Vs and a substrate voltage Vb are used in common by four memory cells M00, M01, M10 and M11. The control gates of the memory cells M00 and M01 are connected in common to a row line W0 while the control gates of the memory cells M10 and M11 are connected in common to a row line W1, and the drain electrodes of the memory cells M00 and M10 are connected in common to a column line D0 while the drain electrodes of the memory cells M01 and M11 are connected in common to a column line D1.
The threshold value of each memory cell, viewed from its control gate, differs, depending on whether electrons have accumulated at its floating gate. That is, when no electrons have accumulated at a cell""s floating gate, the threshold value viewed from its control gate is reduced, and when electrons have accumulated at the cell""s floating gate, the threshold value viewed from its control gate is increased. This cell characteristic makes the nonvolatile storage of information possible.
An explanation will now be given, while referring to FIG. 17, of the voltages that are applied to the electrodes of the memory cell M00 in FIG. 11 during the data reading, the data programming (writing) and the data erasing processes.
First, when data are to be read from the memory cell M00, as is shown in FIG. 17 the voltage set for the row line W0 is 5 V, for the row line W1 is 0 V and for the column line D0 is 1 V, while the column line D1 is open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 0 V. Thus, upon the application of 5 V to the control gate of the memory cell M00 and 1 V to the drain, the memory cell transistor is rendered conductive if the threshold value of the memory cell M00 is low (equal to or below 5 V), or is rendered non-conductive if the threshold value of the memory cell M00 is high (above 5 V). The conductive/non-conductive control is performed in accordance with whether a reading circuit (not shown) detects the flowing of a drain current.
When the memory cell M00 is to be programmed, as is shown in FIG. 17 the voltage set for the row line W0 is 10 V, for the row line W1 it is 0 V and for the column line D0 it is 6 V, while the column line D1 is open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 0 V. Thus, since a voltage of 10 V is applied to the control gate of the memory cell M00 and a voltage of 6 V is applied to the drain, a hot carrier is injected into the floating gate of the memory cell M00, and the threshold value of the memory cell M00 is increased as described above.
For erasing data, there are a xe2x80x9csubstrate erasing method,xe2x80x9d for discharging, to the substrate, the electrons accumulated at the floating gate, and a xe2x80x9csource-gate erasing method,xe2x80x9d for discharging the accumulated electrons to the source. According to the substrate erasing method, as is shown in FIG. 17 the voltage set for both the row lines W0 and W1 is xe2x88x9210 V, while the column lines D0 and D1 and the source voltage Vs are open and the voltage set for the substrate voltage Vb is 10 V. Thus, since a voltage of xe2x88x9210 V is applied to the control gate of each memory cell while a voltage of 10 V is applied to the substrate, the electrons accumulated at the floating gate are discharged to the substrate, and not only are the data in the memory cell M00 erased, but the data in all the other memory cells are also erased, collectively. According to the source-gate erasing method, as is shown in FIG. 17 the voltage set for both the row lines W0 and W1 is xe2x88x9210 V, while the column lines D0 and d1 are open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 10 V. Thus, since a voltage of xe2x88x9210 V is applied to the control gate of each memory cell and a voltage of 10 V is applied to the source, the electrons accumulated at the floating gate are discharged to the source, and data in all the memory cells are collectively erased.
The substrate erasing method and the source-gate erasing method differ greatly in that, for the substrate erasing method, the substrate voltage Vb must be a positive high voltage, while for the source-gate method, the substrate voltage Vb is 0 V both for data programming and for data erasing. This difference is reflected in the device structures used for the two methods.
That is, the device structure appropriate for the substrate erasing method is as shown in FIG. 12, and the device structure appropriate for the source-gate erasing method is as shown in FIG. 13.
In the structure in FIG. 12, an N well 2 is formed in a P semiconductor substrate 1, a P well 3 is formed in the N well 2, and a memory cell is formed in the P well 3. An N diffusion layer 4 is formed in the N well 2, while a P diffusion layer 5, an N source diffusion layer 6 and an N drain diffusion layer 7 are formed in the P well 3. A floating gate 8 and a control gate 9 are provided above a channel between the N source diffusion layer 6 and the N drain diffusion layer 7. The individual regions are defined by field insulating films 10.
Since with this arrangement a positive voltage can be applied to the substrate, this structure is appropriate for the substrate erasing method.
In the structure in FIG. 13, the N well 2 and the P well 3 are not included, and a memory cell transistor is formed directly in a P semiconductor substrate 1. Since with this arrangement a positive voltage can not be applied to the substrate, this structure is appropriate for the source-gate erasing method. In this structure, a voltage of 0 V is constantly applied to the substrate.
According to either method, since as is described above the erasing of data is performed collectively for a plurality of memory cells, the erasing level differs for each memory cell. This means variances in the threshold voltages of the memory cells are produced after the data are erased, and a negative threshold value may be held by some memory cells.
As is described above, information is stored in a memory cell in accordance with whether during the reading process the threshold value held by the pertinent memory cell is equal to or lower than the row line voltage. Since in a flash memory a selection transistor is not provided for each memory cell, the threshold value must, at the least, be positive. If the threshold value is negative, the memory cell is rendered conductive, even when it is not selected, and selecting the memory cell is a meaningless effort.
Specifically, when the threshold value of a memory cell falls and becomes negative, during the reading process, deterioration of the reading characteristic occurs. Assume that the threshold value of the memory cell M10 in FIG. 11 falls and becomes negative, and that data are to be read from the memory cell in the programmed state (the cell has a high threshold value). Since the memory cell M00 is in the programmed state, it is not rendered conductive even upon the application of a read voltage (5 V) to the row line W0. However, the memory cell 10, which has a negative threshold value, is rendered conductive, even though the voltage at the row line W1 is 0 V, and as a result, a current flows from the column line D0, via the memory cell M10, to the source. Therefore, the reading circuit may erroneously determine that the memory cell M00 is in the erased state (the cell has a low threshold value).
The presence during the programming process of a memory cell that has a negative threshold voltage also causes the program characteristic to be deteriorated. Similarly, assume that the threshold voltage of the memory cell M10 is negative and that the memory cell M00 is to be programmed. Even though the voltage at the row line W1 is 0 V, the memory cell M10, which has a negative threshold value, is rendered conductive, and a current flows from the column line D0, via the memory cell M10, to the source. Therefore, the voltage at the column line D0 drops, and either the programming of the memory cell M00 is unsatisfactory, or, in some cases, a programming disabled state is entered. Further, since the drain voltage (6 V) during the programming process is higher than the drain voltage (1 V) during the reading process, compared with the reading process, a larger current, a leak, flows across the memory cell that has the negative threshold value during the programming process. Thus, drastic deterioration of the programming characteristic occurs.
A method for preventing the deterioration of the programming characteristic, as a result of the presence of a memory cell having a negative threshold voltage, is disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 5-210991.
According to the method described in this publication, during the programming process a negative voltage is applied to the control gate of a memory cell that is not to be programmed. Specifically, as is shown in FIG. 14, a voltage of 10 V is applied to a row line W0 by a row decoder 34 to apply 10 V to the control gate of a memory cell M00 that is to be programmed, while a negative voltage of xe2x88x920.5 V is applied to a row line W1 to load a negative voltage into the control gate of a memory cell M10 that is not to be programmed. Thus, even when the threshold voltage of the memory cell M10, which is not a programming target, falls to a negative value, the probability is greater that the memory cell M10 can be rendered non-conductive, and that the programming of the memory cell M00 can be performed correctly.
Another method for preventing the deterioration of the programming characteristic, as a result of the presence of a memory cell having a negative threshold voltage, is disclosed, for example, in Japanese Unexamined Patent Publication No. Sho 57-205895.
According to the method disclosed in this publication, during the programming process, the voltage set for a source voltage Vs is higher than the voltage at the control gate of a memory cell that is not to be programmed. Specifically, as is shown in FIG. 15, assuming that a memory cell M00 is a programming target, the voltage set for a column D0 is 6.5 V, a column D1 is open, the voltages set for row lines W0 and W1 are 10.5 V and 0 V, respectively, and the voltage set for a source voltage Vs is 0.5 V. Thus, because the gate-source voltage during the programming process is xe2x88x920.5 V, even when the threshold value for a memory cell M10 that is not a programming target falls to a negative value, as with the method described in Japanese Unexamined Patent Publication No. Hei 5-210991, the probability is greater that the memory cell M10 can be rendered non-conducive, and that the programming for the memory cell M00 can be performed correctly.
It should be noted that each of the voltages applied to the control gate, the source and the drain of the memory cell M00, which is the programming target, is increased by 0.5 V, as shown in FIG. 17, the relationship between the control gate voltage, the source voltage and the drain voltage of the memory cell M00 is maintained.
With the method in FIG. 14 that is disclosed in Japanese Unexamined Patent Publication No. Hei 5-210991, however, not only is a program voltage supply circuit 30 required, but also a negative voltage supply circuit 32 for providing a voltage of xe2x88x920.5 V must be supplied. Furthermore, the row decoder 343 must also apply a voltage of 10 V to a row line to be selected, and a voltage of xe2x88x920.5 V to a row line that is not selected. Therefore, the control mechanism is complicated, and as a result, the size of the circuit is increased. Furthermore, since during the actual program processing a negative voltage must be applied to all the Lines that are not selected, and for this a wait time is required, the total programming time is increased.
In addition, according to the method in FIG. 15 that is disclosed in Japanese Unexamined Patent Publication No. Sho 57-205895, the relationship shown in FIG. 17 is maintained for the control gate voltage, the source voltage and the drain voltage of the memory cell that is the programming target. So that when taking into consideration the relationship with the substrate voltage, the voltage difference is increased. Specifically, the difference between the substrate voltage and the drain voltage is 6 V in FIG. 17, while the difference provided by the method in the referenced publication is 6.5 V.
This means that the ability to withstand the voltage that the diffusion layer requires must be increased. Thus, when taking into account the increase in the impurity density of the substrate, which is required to prevent punch through, since the development of the high definition technique it has been difficult to increase the ability of the drain diffusion layer to withstand damage. And therefore, the method disclosed in the referenced publication may reduce the reliability of a product.
It is, therefore, one objective of the present invention to provide a nonvolatile semiconductor memory device that minimizes the size of a circuit and that prevents the deterioration of a programming characteristic, which is due to the presence of a memory cell having a negative threshold voltage, and a programming method therefor.
It is another objective of the present invention to provide a nonvolatile semiconductor memory device that suppresses the extension of a programming time and that prevents the deterioration of a programming characteristic, which is due to the presence of a memory cell having a negative threshold voltage, and a programming method therefor.
It is an additional objective of the present invention to provide a nonvolatile semiconductor memory device that does not require an increase in the ability of a drain diffusion layer to withstand and prevent the deterioration of a programming characteristic, which is due to the presence of a memory cell having a negative threshold voltage, and a programming method therefor.
According to the present invention, a nonvolatile semiconductor memory device is provided wherein, during a programming process, a source voltage and a substrate voltage, for each of a plurality of memory cell transistors, are set to a positive voltage. Thus, the deterioration of a programming characteristic, which is caused by the presence of a memory cell having a negative threshold value, can be prevented, and the above objectives can be achieved.